`timescale 1ns/1ns

module logic_shift_tb;
    reg signed [7:0] i_a = 8'b1011_0111;
    reg [2:0] i_bit = 0;
    
    wire signed [7:0] o_sll,
            o_srl;

    initial begin
        $dumpfile("output/logic_shift_tb.vcd");
        $dumpvars(0, logic_shift_tb);
    end
    
    initial while(i_bit<7) #20 i_bit = i_bit + 1'b1;
    initial #160 $stop;
    
    logic_shift logic_shift_inst(
        .iA   (i_a),
        .iBit (i_bit),
        .oSLL (o_sll),
        .oSRL (o_srl)
    );
 
endmodule